1. Field of the Invention
The present invention relates generally to memory control apparatus, and more particularly is directed a memory control apparatus which is adapted to convert an input video signal to an output video signal by writing the input video signal in a video memory while concurrently reading the output video signal from the video memory.
2. Description of the Prior Art
Memory control apparatus have been proposed for processing a video signal, for example, a standard NTSC television system video signal, so as to display a variety of images on a television or display screen.
An example of such memory control apparatus is one providing a so-called picture-in-picture function, which as shown in FIG. 1A, allows simultaneous displaying of a parent picture PIC1 which, for example, is a first input image reproduced from a video tape recorder (VTR), and appears over the whole area of a display screen DIP, and of a child picture PIC2 which, for example, is a second input image corresponding to a broadcast video signal and is suitably reduced, for example, by a factor of four so as to appear only on a part of the screen. By means of such picture-in-picture function it is possible to confirm the image being reproduced by the VTR while viewing an image of a broadcast program being presently received.
Another example of a memory control apparatus for processing a video signal is one having a multi-screen function which, as shown in FIG. 1B, divides the display screen DIP into four reduced screen areas PIC11 to PIC14, that is, divides the display screen DIP in two both longitudinally (in the vertical direction) and laterally (in the horizontal direction), and which displays on the screen areas PIC11 to PIC14 four different images derived from four different television channels (for example, the first, the third, fourth and sixth channels), respectively, or four still images sequentially derived from a single moving image. The proposed memory control apparatus can be widely utilized by providing the same with many displaying functions in addition to those described above.
In accordance with conventional image converting techniques for effecting picture-in-picture, multi-screen or other like functions, an input video signal is converted to digital video data, the converted digital video data is written in a video memory while the written video data is read from the video memory to display the read data as an image on the display screen, thereby making it possible to easily effect the processings required for reducing or enlarging an image, superimposing a plurality of images, displaying a moving image and a still image on the screen, or the like.
When a video signal to be displayed on the display screen DIP is generated by writing the video data in the video memory while concurrently reading the video data written in the video memory, as described above, if a write address signal for writing input video data in the video memory is not synchronized with a read address signal for reading the output video data from the video memory, or even when these two address signals are synchronized with each other, if the input video data is processed to generate output video data for displaying a reduced or enlarged image, there is the possibility that the read address will overtake the write address or vice versa, in which case there will be a disturbance in the output video data and hence in the displayed picture.
Considering now, with respect to FIG. 2, a specific example in which video data constituting one frame portion (formed of two field portions) are written in a video memory from the initial address AD.sub.O to the last address AD.sub.MAX in respective write cycles from a time WCK.sub.O to a time WCK.sub.MAK, as indicated by a write operation curve FRM.sub.W, while the video data written in the video memory from the initial address AD.sub.O to the last address AD.sub.MAX are concurrently read therefrom in respective read cycles T.sub.R from a time RCK.sub.O to a time RCK.sub.MAX as indicated by a read operation curve FRM.sub.R, it will be appreciated that, if the write operation curve FRM.sub.W crosses the read operation curve FRM.sub.R at a crossing point P.sub.X1, an address AD.sub.X1 specified by the read address signal overtakes an address specified by the write address signal at the time CK.sub.X1.
When one frame portion of video data representative of an image of a circle K2 shown in solid lines in FIG. 3 is written in the addresses AD.sub.O to AD.sub.MAX, along the write operation curve FRM.sub.W of the video memory in which video data representative of an image of a circle K1 shown in dotted lines in FIG. 3 has been already written so as to display a movement of the circle, the displayed image is disturbed.
More specifically, if the data of the circle K2 is written in the video memory along the write operation curve FRM.sub.W (FIG. 2) at a time when the data of the circle K1 previously written in the video memory are being concurrently read out along the read operation curve FRM.sub.R, the video data of the circle K2 written in place of the data of the circle K1 in the period between the times WCK.sub.O and CK.sub.X1 is read out in a period between times RCK.sub.O to CK.sub.X1 before the cross-over point P.sub.X1, as shown in FIG. 3B.
On the other hand, since the read address overtakes the write address in a period between the times CK.sub.X1 and RCK.sub.MAX of the read operation curve FRM.sub.R, the video data of the circle K2 is written in the video memory after the video data which had been stored before the video data of the circle K2 was written in the video memory along the write operation curve FRM.sub.W (that is, the video data of the circle K1 of the preceding frame). Consequently, the video data read out from the video memory represents the circle K1.
As is apparent from FIG. 3B, if the address specifying rate is different for writing and reading, for example, if the write address signal is not synchronized with the read address signal, the write operation curve FRM.sub.W and the read operation curve FRM.sub.R inevitably cross each other, and the contents of the video data at the address corresponding to the cross-over point P.sub.X1 are displaced so that the displayed image is disturbed, for example, relatively shifted laterally above and below the line LIN.sub.Xl.
Although displacement in the image is not so conspicuous in a still image, it causes unpleasant disturbance in a moving image.
FIGS. 2, 3A and 3B show the case where the address specified by the read address signal overtakes the address specified by the write address signal. On the contrary, if an address specified by the write address signal overtakes an address specified by the read address signal at a cross-over point P.sub.X2 at a time CK.sub.X2, as shown in FIGS. 4, 5A and 5B which correspond to FIGS. 2, 3A and 3B, disturbance again occurs in the displayed image, as on FIG. 5B.